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1. features ? low-voltage and standard-voltage operation ? 1.8 (v cc = 1.8v to 5.5v) ? internal organization ? 64 x 16 ? three-wire serial interface ? 2 mhz clock rate (5v) compatibility ? self-timed write cycle (5 ms max) ? high reliability ? endurance: 1 million write cycles ? data retention: 100 years ? 8-lead pdip, 8-lead jedec soic, and 8-lead tssop packages ? lead-free/halogen-free devices 2. description the at93c46e provides 1024 bits of serial electrically-erasable programmable read- only memory (eeprom) organized as 64 word s of 16 bits each. the device is opti- mized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at 93c46e is availabl e in space-saving 8- lead pdip, 8-lead jedec soic, and 8-lead tssop packages. the at93c46e is enabled through the chip select pin (cs) and accessed via a three- wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output do pi n. the write cycle is completely self-timed and no separate erase cycle is required before write. the write cycle is only enabled when the part is in the erase/write enable state. when cs is brought high following the initiation of a write cycle, the do pin outputs the ready/busy status of the part. the at93c46e is available in 1.8v (1.8v to 5.5v) version. table 2-1. pin configuration pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply nc no connect three-wire serial eeprom 1k (64 x 16) at93c46e rev. 5207d?seepr?1/08 1 2 3 4 8 7 6 5 c s s k di do vcc nc nc gnd 1 2 3 4 8 7 6 5 c s s k di do vcc nc nc gnd 1 2 3 4 8 7 6 5 c s s k di do vcc nc nc gnd 8-lead pdip 8-lead soic 8-lead tssop
2 5207d?seepr?1/08 at93c46e figure 2-1. block diagram note: this parameter is characterized and is not 100% tested. absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma memory array 64 x 16 data regi s ter mode decode logic clock generator output buffer addre ss decoder table 2-2. pin capacitance (1) applicable over recommended operating range from t a = 25c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (do) 5 pf v out = 0v c in input capacitance (cs, sk, di) 5 pf v in = 0v
3 5207d?seepr?1/08 at93c46e note: 1. v il min and v ih max are reference only and are not tested. table 2-3. dc characteristics applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i sb1 standby current v cc = 1.8v cs = 0v 0.4 1.0 a i sb2 standby current v cc = 2.7v cs = 0v 6.0 10.0 a i sb3 standby current v cc = 5.0v cs = 0v 10.0 15.0 a i il input leakage v in = 0v to v cc 0.1 1.0 a i ol output leakage v in = 0v to v cc 0.1 1.0 a v il1 (1) v ih1 (1) input low voltage input high voltage 2.7v v cc 5.5v ? 0.6 2.0 0.8 v cc + 1 v v il2 (1) v ih2 (1) input low voltage input high voltage 1.8v v cc 2.7v ? 0.6 v cc x 0.7 v cc x 0.3 v cc + 1 v v ol1 v oh1 output low voltage output high voltage 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v i oh = ? 0.4 ma 2.4 v v ol2 v oh2 output low voltage output high voltage 1.8v v cc 2.7v i ol = 0.15 ma 0.2 v i oh = ? 100 a v cc ? 0.2 v
4 5207d?seepr?1/08 at93c46e note: 1. this parameter is ensured by characterization. 3. functional description the at93c46e is accessed via a simple and ve rsatile three-wire serial communication inter- face. device operation is controlled by seven instructions issued by the host processor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ?1?) followed by the appropriate op code and the desired memory address location. table 2-4. ac characteristics applicable over recommended operating range from t a = ? 40 c to + 85 c, v cc = +2.7v to + 5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter test condition min typ max units f sk sk clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 0 0 0 2 1 0.25 mhz t skh sk high time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t skl sk low time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t cs minimum cs low time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t css cs setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 50 50 200 ns t dis di setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 100 400 ns t csh cs hold time relative to sk 0 ns t dih di hold time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 100 400 ns t pd1 output delay to ?1? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t pd0 output delay to ?0? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t sv cs to status valid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t df cs to do in high impedance ac test cs = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 150 400 ns t wp write cycle time 0.1 3 5 ms endurance (1) 5.0v, 25 c1mwrite cycle
5 5207d?seepr?1/08 at93c46e read (read): the read (read) instruction contains the address code for the memory loca- tion to be read. after the instruction and address are decoded, data from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic ?0?) precedes the 16- bit data output string. erase/write enable (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) stat e when power is first applied . an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the ewen state, programming remains enabled until an ewds instruc- tion is executed or v cc power is removed from the part. erase (erase): the erase (erase) instruction program s all bits in the specified memory location to the logical ?1? stat e. the self-timed eras e cycle starts once th e erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?1? at pin do indicates that the selected memory location has been erased and the part is ready for another instruction. write (write): the write (write) instruction contains the 16 bits of data to be written into the specified memory location. the self-timed programming cycle, t wp , starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?0? at do indi- cates that programming is still in progress. a logi c ?1? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self-timed programming cycle, t wp . erase all (eral): the erase all (eral) instruction programs every bit in the memory array to the logic ?1? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the eral instruction is valid only at v cc = 5.0v 10%. write all (wral): the write all (wral) instruction pr ograms all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the wral instruction is valid only at v cc = 5.0v 10%. table 3-1. instruction set for the at93c46e instruction sb op code address comments x 16 read 1 10 a 5 ? a 0 reads data stored in memory, at specified address ewen 1 00 11xxxx write enable must precede all pr ogramming modes erase 1 11 a 5 ? a 0 erase memory location a n ? a 0 write 1 01 a 5 ? a 0 writes memory location a n ? a 0 eral 1 00 10xxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxx writes all memory locations. valid only at v cc = 4.5v to 5.5v ewds 1 00 00xxxx disables all programming instructions
6 5207d?seepr?1/08 at93c46e erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction disables all pr ogramming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds instructions and can be executed at any time.
7 5207d?seepr?1/08 at93c46e 4. timing diagrams figure 4-1. synchronous data timing note: 1. this is the minimum sk period. figure 4-2. read timing s (1) table 4-1. organization key for timing diagrams i/o at93c46e x 16 a n a 5 d n d 15 high impedance t cs
8 5207d?seepr?1/08 at93c46e figure 4-3. ewen timing (1) note: 1. requires a minimum of nine clock cycles. figure 4-4. ewds timing (1) note: 1. requires a minimum of nine clock cycles. figure 4-5. write timing cs 11 ... 00 1 sk di t cs cs t cs sk di 1 0 000 ... sk cs t cs t wp 11 a n d n 0a0d0 ... ... di do high impedance busy ready
9 5207d?seepr?1/08 at93c46e figure 4-6. wral timing ( (1) ),( (2) ) notes: 1. valid only at v cc = 4.5v to 5.5v. 2. requires a minimum of nine clock cycles. figure 4-7. erase timing figure 4-8. eral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. cs sk di do high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0 sk 1 1 ... 1 cs di a n t cs t sv t df t wp a n-1 a n-2 a0 check status standby ready busy do high impedance high impedance sk cs di 1 1 00 0 do high impedance high impedance ready busy check status standby t wp t cs t sv t df
10 5207d?seepr?1/08 at93c46e notes: 1. ?b? denotes bulk. 2. ?-t? denotes tape and reel. soic = 4k per reel. tssop = 5k per reel. at93c46e ordering information ordering code package operation range at93c46e-pu (bulk form only) 8p3 lead-free/halogen-free/ industrial temperature ( ? 40 c to 85 c) AT93C46EN-SH-B (1) (nipdau lead finish) 8s1 at93c46en-sh-t (2) (nipdau lead finish) 8s1 at93c46e-th-b (1) (nipdau lead finish) 8a2 at93c46e-th-t (2) (nipdau lead finish) 8a2 package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 0.170" wide, thin small outline package (tssop) options ? 1.8 low voltage (1.8v to 5.5v)
11 5207d?seepr?1/08 at93c46e part marking scheme: at93c46e 8-pdip at93c46e 8-soic top mark seal year y = seal year ww = seal week | seal week 6: 2006 0: 2010 02 = week 2 | | | 7: 2007 1: 2011 04 = week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : a t m l u y w w 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = week 50 4 6 e 1 52 = week 52 |---|---|---|---|---|---|---|---| * lot number lot number to use all characters in marking |---|---|---|---|---|---|---|---| | bottom mark pin 1 indicator (dot) no bottom mark top mark seal year y = seal year ww = seal week | seal week 6: 2006 0: 2010 02 = week 2 | | | 7: 2007 1: 2011 04 = week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : a t m l h y w w 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = week 50 4 6 e 1 52 = week 52 |---|---|---|---|---|---|---|---| * lot number lot number to use all characters in marking |---|---|---|---|---|---|---|---| | bottom mark pin 1 indicator (dot) no bottom mark
12 5207d?seepr?1/08 at93c46e at93c46e 8-tssop top mark pin 1 indicator (dot) y = seal year ww = seal week | 6: 2006 0: 2010 02 = week 2 |---|---|---|---| 7: 2007 1: 2011 04 = week 4 * h y w w 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013 :: : :::: :: 4 6 e 1 50 = week 50 |---|---|---|---|---| 52 = week 52 bottom mark |---|---|---|---|---|---|---| c 0 0 |---|---|---|---|---|---|---| a a a a a a a |---|---|---|---|---|---|---| <- pin 1 indicator
13 5207d?seepr?1/08 at93c46e 5. packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
14 5207d?seepr?1/08 at93c46e 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0? ? 8? ? ? e e 1 1 n n top view top view c c e1 e1 end view a a b b l l a1 a1 e e d d side view side view
15 5207d?seepr?1/08 at93c46e 8a2 - tssop title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 8 a2 tnr c 8 a2, 8 -le a d, 4.4mm body, pl as tic thin s hrink s m a ll o u tline p a ck a ge (t ss op) 10/29/0 8 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d 2.90 3 .00 3 .10 2, 5 e 6.40 b s c e1 4. 3 0 4.40 4.50 3 , 5 a ? ? 1.20 a2 0. 8 0 1.00 1.05 b 0.19 ? 0. 3 0 4 e 0.65 b s c l 0.45 0.60 0.75 l1 1.00 re 3 note s : 1. thi s dr a wing i s for gener a l inform a tion only. refer to jedec dr a wing mo-15 3 , v a ri a tion aa, for proper dimen s ion s , toler a nce s , d a t u m s , etc. 2. dimen s ion d doe s not incl u de mold fl as h, protr us ion s or g a te bu rr s . mold fl as h, protr us ion s a nd g a te bu rr s s h a ll not exceed 0.15 mm (0.006 in) per s ide. 3 . dimen s ion e1 doe s not incl u de inter-le a d fl as h or protr us ion s . inter-le a d fl as h a nd protr us ion s s h a ll not exceed 0.25 mm (0.010 in) per s ide. 4. dimen s ion b doe s not incl u de d a m ba r protr us ion. allow ab le d a m ba r protr us ion s h a ll b e 0.0 8 mm tot a l in exce ss of the b dimen s ion a t m a xim u m m a teri a l condition. d a m ba r c a nnot b e loc a ted on the lower r a di us of the foot. minim u m s p a ce b etween protr us ion a nd a dj a cent le a d i s 0.07 mm. 5. dimen s ion d a nd e1 to b e determined a t d a t u m pl a ne h. s ide view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indic a tor thi s corner e e
16 5207d?seepr?1/08 at93c46e revision history doc. rev. date comments 5207d 1/2008 removed ?preliminary? status 5207c 11/2007 modified ?max? value on ac characteristics table 5207b 8/2007 modified part marking scheme tables 5207a 1/2007 initial document release
5207d?seepr?1/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support s_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ?2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others, are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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